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functional block diagram analog front end 16:1 decimation comb filter system timing and control 4:1 decimation fir filter serial interface AD776 5 4 1 13 9 11 10 agnd clkin fsi sf doe dout clk 20 2 3 ain+ ain refin 19 refout 8 6 fsel dv dd 18 av dd dgnd dout 6.4mhz 12.8mhz 3.2mhz 6.4mhz 7 12 fso x u m v ref rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 16-bit 100 ksps oversampling adc AD776 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features monolithic 16-bit sigma-delta adc third-order noise shaping 96 db dynamic range 90 db snr 16-bit 100 khz output from fir filter 12-bit 400 khz output from comb filter no missing codes <0.001 db in-band ripple applications digital audio disk/tape voice bandwidth communications adc support for adsp-21xx high accuracy measurement systems product description the AD776 is a 16-bit sigma-delta oversampled adc, incorpo- rating a 1-bit thir d-order modulator and di gital decimation filter. an on-chip voltage reference circuit is also included. the AD776 does not generally require the use of sample-hold circuits or complex antialiasing filters as a result of its sigma- delta architecture. the output is available both before and after the final finite impulse response (fir) decimation filter. this provides the flexibility of optimizing conversion speed or dy- namic range: 12-bit/400 khz (from the comb filter) or 16-bit/ 100 khz (from the fir filter). the serial port provides easy in- terface with a variety of standard processors including the adsp-21xx. the AD776 is specified for ac (or dynamic) parameters such as snr, thd and imd which are important in signal process- ing and audio applications. third order noise shaping is employed using 64 times oversam pling to pro vide 90 db snr and C100 db peak spurious component for signal bandwidths up to 45 khz. the AD776 operates from a single +5 v supply and typically consumes 350 mw during conversion. the device is packaged in 20-pin ceramic dip (cerdip) and is offered in an industrial temperature grade (C40 c to +85 c). product highlights 1. analog front end. the analog input is differential providing increased signal swing, increased power supply rejection ra- tio, and reduced sensitivity to clock jitter. since the input sig- nal is oversampled by a factor of 64, a c omplex antialiasing filter is not needed. 2. flexible digital interface. the AD776 has three output pins for the serial interface: 1) serial data out (dout), 2) frame sync out (fso), and 3) serial clock out (dout clock). the serial port can interface with general purpose dsps such as the adsp-21xx, tms320xx, and dsp56001/2 without additional glue logic. 3. inherently self-sampling. the AD776 needs no external sample-and-hold amplifier to capture and freeze the analog input while the conversion takes place. 4. speed/performance options. in addition to the standard 16-bit resolution at 100 khz, the output of the comb filter can be accessed to provide 12-bit resolution at 400 khz.
AD776Cspecifications rev. a C2C (t min to t max ; av dd , dv dd = +5 v, fir filter output mode unless otherwise noted) parameter min typ max units resolution 16 bits temperature range C40 +85 c total harmonic distortion (thd) 1, 2, 3 C80 C83 db 0.01 0.003 % signal-to-noise ratio (snr) 1, 2 , f s = 48 ksps 88 90 db signal to noise ratio (snr) 1, 2 , f s = 100 ksps 86 db comb filter mode, clkin = 12.8 mhz 72 db peak spurious or peak harmonic component C100 db intermodulation distortion (imd) 4 2nd order products C102 db 3rd order products C98 db voltage reference output (v ref ) (av dd 0.4) C 4% av dd 0.4 v (av dd 0.4) + 4% v maximum analog input range 5 2 v ref C 0.5 v p-p maximum input signal 6 0.5 v ref v p-p dc accuracy 1 differential nonlinearity 0.5 lsb inl 2 lsb gain error 1.0 % midscale error 0.5 % digital filter characteristics passband ripple 0.001 db stopband attenuation C96 db power supply requirements 7 analog supply voltage (av dd ) 4.5 5.0 5.5 v digital supply voltage (dv dd ) 4.5 av dd v analog supply current 20 ma digital supply current 20 ma power consumption 8 300 400 mw power supply rejection 9 70 db digital specifications parameter test conditions min typ max units logic inputs v ih high level input voltage 2.0 v dd v v il low level input voltage C0.5 0.8 v i ih high level input current v ih = v dd 1 m a i il low level input current v il = 0 v 1 m a c in input capacitance 10 pf i z hi-z input current for sdo 10 m a logic outputs v oh high level output voltage i oh = 0.4 ma 2.4 v v ol low level output voltage i ol = 2.0 ma 0.5 v notes 1 at +25 c. 2 analog input = 1.2 v rms @ 10 khz, v common mode = 2.5 v, clkin = 6.4 mhz. 3 thd performance can be improved, depending upon the application, by making slight adjustments to the dc common-mode voltage at the analog inputs. 4 imd measured at f s = 48 khz and using 61.6 hz and 986.4 hz as the input tones (sum of the two peaks added to be C3 db fs). 5 applied differentially between ain+ and ainC. 6 the input signal may be centered at any choice of dc offset voltage as long as peak values are bounded by the maximum analog input range value. performance may be improved by reducing the maximum input signal by 3 db. for nominal operation, 2.5 v dc offset is recommended. 7 the AD776 may be operated from a single +5 v supply. 8 av dd , dv dd = 5.5 v; f = 12.8 mhz; t a = +85 c. 9 with external voltage reference. specifications subject to change without notice.
AD776 rev. a C3C timing characteristics symbol parameter min max units f clock in frequency 1 12.8 mhz t clk clock in period (= 1/f) 78 1000 ns t d duty cycle 0.475 t clk 0.525 t clk ns t cl clock low 37 41 ns l 475 525 ns 2 t ch clock high 37 41 ns l 475 525 ns 2 t r rise time 5 ns t f fall time 5 ns t fss frame sync input setup time 20 78 ns t fsh frame sync input hold time 20 C 3 ns t fsil frame sync input low 2 t clk t dod data output clock delay 25 75 ns t dop data output clock period 156 ns 1, 4 312 ns 1, 5 t fsosc fso setup time before clkin 130 ns 5 t fsohc fso hold time after clkin 130 ns 5 t fsosd fso setup time before dout clk 110 ns 5 t fsohd fso high to dout clk rising edge 110 ns 5 t io fsi to fso delay 1 t clk 4 5t clk 5 t dsu data output setup time 40 ns 4 130 ns 5 t dh data output hold time 40 ns 4 130 ns 5 t dd data delay time 0 20 ns t df data float time 0 20 ns notes 1 clkin = 12.8 mhz. 2 clkin = 1 mhz. 3 fsi must be deasserted for at least two clkin periods prior to being asserted. 4 comb filter mode. 5 fir filter mode. specifications subject to change without notice. (av dd , dv dd = +5 v 6 10%, t min to t max )see figures 14 through 18. absolute maximum ratings* av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7.0 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7.0 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 v digital inputs to dgnd . . . . . . . . . . . . . . . . C0.3 v to dv dd analog inputs to agnd . . . . . . . . . . . . . . . . C0.3 v to av dd refin to agnd . . . . . . . . . . . . . . . . . . . . . C0.3 v to +2.5 v soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300 c storage temperature . . . . . . . . . . . . . . . . . . C55 c to +150 c *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD776 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
AD776 C4C rev. a AD776 pin description symbol pin number type name and function agnd 1 analog ground. return current for analog front end. no internal connection to dgnd. ain+ 2 i analog signal input. noninverting terminal. ainC 3 i analog signal input. inverting terminal. clkin 4 i clock in. this ttl compatible input accepts clock frequencies in the range of 1.0 mhzC12.8 mhz, with the output sample rate of the AD776 equal to clkin divided by 128 in fir filter mode and 32 in comb filter mode. fsi 5 i frame sync input. fsi is an optional control pin used to synchronize internal cir- cuits and to start or reset the serial output data. if fsi is grounded, frame syncs will be automatically generated internally. when fsi is brought high, serial data is presented at the output (doutpin 11). the purpose of fsi is to control exter- nally the phasing of the a/d conversion process. fsi should be a periodic signal occurring every 16 dout clk clock cycles in the 12-bit/400 khz mode and every 32 dout clk clock cycles in the 16-bit/100 khz mode. when utilized, fsi must be synchronized to clkin as defined in the timing specification (see figure 17). fsi allows multiple AD776s to be synchronized using a common frame sync source, requiring a common clkin signal. fsel 6 i filter select. fsel = 0 selects fir output. fsel = 1 selects comb filter ou tput. sf 7 i serial format. selects output format of dout and fso when fsel = 0. see figures 14b and 15b. dv dd 8 +5 v 10%. digital power supply. fso 9 o frame sync output. indicates beginning of serial data transmission on dout. see timing diagrams. dout clk 10 o serial data clock. see figures 14a and 14b. in the fir filter output mode (fsel = 0), dout clk is clkin divided by four; in the comb filter output mode (fsel = 1), dout clk is clkin divided by two. dout 11 o data output. serial data is transmitted msb first, twos complement format, once per fso cycle with the data synchronous with dout clk. doe 12 i data output enable. serial data (pin 11) is an active output when doe = 0. serial data is three stated when doe = 1. dgnd 13 digital ground. return current for digital circuitry and pad drivers. tp3, tp2, tp1, tp0 14, 15, 16, 17 test points. these pins must be connected to dgnd. av dd 18 +5 v 10%. analog power supply. refout 19 o internal reference output. nominally +2 v with av dd = +5.0 v. refin 20 i reference input. +2 v maximum. i = input o = output pin configuration 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 top view (not to scale) agnd ain+ ain clkin fsi fsel sf dv dd fso dout clk refin refout av dd tp0 tp1 tp2 tp3 dgnd dout doe AD776 ordering guide temperature package package model range description option AD776aq C40 c to +85 c 20-pin cerdip q-20
AD776 rev. a C5C general overview the AD776 is a single supply (+5 v) adc providing simple analog and digital interface requirements. a minimal number of external connections are required to achieve the specified performance: 1. power 2. grounds 3. clocking 4. input buffer circuit these points will be further explored in the application infor- mation section. theory of operation the AD776 differs from traditional multibit adcs through its use of sigma-delta conversion architecture. a 1-bit analog-to- total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the harmonic components to the rms value of a full-scale input signal and is expressed in percent (%) or decibels (db). signal-to-noise ratio (snr) signal-to-noise ratio (snr) is defined to be the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the passband. intermodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfa + nfb, where m, n = 0, 1, 2, 3. . . . intermodulation terms are those for which m or n is not equal to zero. for example, the second or- der terms are (fa+fb) and (faCfb), and the third order terms are (2fa+fb), (2faCfb), (fa+2fb) and (faC2fb). the imd products are expressed as the decibel ratio of the rms sum of the mea- sured input signals to the rms sum of the distortion terms. the two signals applied to the converter are of equal amplitude and the imd products are normalized to a 0 db input signal. differential nonlinearity (dnl) in an ideal adc, code transitions are one lsb apart. differen- tial nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. integral nonlinearity (inl) the ideal transfer function for an adc is a straight line drawn between zero and full scale. the point used as zero oc- curs 1/2 lsb before the most negative code transition. full scale is defined as a level 1 1/2 lsb beyond the most positive code transition. inl is the worst-case deviation of a code center average from the straight line. gain error the last transition should ideally occur at an analog value 1.5 lsb below the nominal full scale. the gain error is the de- viation of the actual difference between the first and last code transition from the ideal difference between the first and last code transition. digital conversion is performed at a very high rate, which redis- tributes quantization noise to beyond the frequency band of interest (see figure 1). the frequency band of interest is denoted by f c , and f s is the sample frequency; f s /2 is the expanded noise spectrum resulting from oversampling. the total noise energy remains constant, but by spreading it over a wider spectrum, the amount in the frequency band of interest is reduced. noise shaping, performed by the modulator, attenuates noise in the signal passband and pushes out the noise energy into the higher frequency range (figure 2). the oversampled signal is pre- sented to the digital filter circuitry for: C sophisticated averaging (filtering). C removing high frequency noise (quantization noise removal). C reducing sampling rate (decimation). midscale error midscale error is the difference between the ideal midscale ana- log input voltage and the actual voltage producing the midscale output code. passband the passband is the region of the frequency spectrum unaf- fected by the attenuation of the decimation filter. in the case of the AD776, the passband is a function of the clkin frequency (see table i). passband ripple passband ripple is defined as the variation in the amplitude response of the converter for input signal frequencies within the passband. stopband the stopband is the region of the frequency spectrum in which the amplitude response is fully attenuated by the digital filter. in the case of the AD776, the stopband is a function of the clkin frequ ency (see table i). stopband attenuation stopband attenuation is defined to be the amount by which spectral components in the stopband are attenuated by the digi- tal filter relative to the full-scale input range of the converter. power supply rejection dc variations in the power supply voltage will affect the mid- scale transition point, resulting in offset error. power supply rejection is the maximum change in the midscale transition point due to a change in power-supply voltage from the nominal value. additionally, there is another power supply variation to consider. ac ripple on the power supplies can couple noise into the adc, resulting in degradation of dynamic performance.
AD776 C6C rev. a the resulting output data stream is presented in a format equivalent to a traditional adc at a much reduced output sample rate. signal spectrum frequency band of interest quantization noise amplitude f c f /2 s frequency figure 1. noise spectrum from oversampling signal spectrum frequency band of interest shaped quantization noise amplitude f c f /2 s frequency transfer function of digital low-pass filter figure 2. noise shaping figure 3 provides a block diagram of the various sections of the AD776. the analog front end is comprised of three differen- tial switched capacitor linear integrators which perform the noise-shaping function. digital filter complexity of the AD776 is reduced by performing the filtering and decimation in two stages. the first section contains a 16:1 decimating comb filter stage with the output presented to a 4:1 decimating low-pass/ compensation fir filter, resulting in a final decimation ratio of 64:1. the decimation function is described in detail in the decimation paragraph. the output data is presented in twos complement, msb first serial data format, providing serial communication to a host processor. this interface uses three dedicated pins: serial data output (dout), frame sync output (fso), and serial clock output (dout clk). the serial interface format of operation is pin selectable. the timing diagrams for the serial interface are described in the digital timing section. analog front end 16:1 decimation comb filter system timing and control 4:1 decimation fir filter serial interface AD776 5 4 1 13 9 11 10 agnd clkin fsi sf doe dout clk 20 2 3 ain+ ain refin 19 refout 8 6 fsel dv dd 18 av dd dgnd dout 6.4mhz 12.8mhz 3.2mhz 6.4mhz 7 12 fso x u m v ref figure 3. block diagram analog front end the integrators of the third-order modulator front end form a differential switched-capacitor network which results in increased signal swing, increased power supply rejection, and reduced sensitivity to clock jitter. due to the nature of switched- capacitor circuits, the input impedance of ain+, ainC, and refin will vary with clock frequency. more information about these inputs is given in table ii and table iii. the AD776 modulator is a third-order noise shaper which re- duces quantization noise in the passband to the 16-bit level. the input signal is sampled at the rate of clkin/4. since the input signal is oversampled by a factor of 64, a complex anti- aliasing filter is not needed; a single-pole rc filter will generally be sufficient. high quality polystyrene or npo ceramic capaci- tors should be used for this filter. digital filter overview the digital filters of the AD776 have two functions: high perfor- mance low-pass filtering and digital decimation. the shaped quantization noise from the output of the modulator is low-pass filtered to reduce the out-of-band noise components to a level which will not alias into the passband during the decimation process. decimation then reduces the data rate to a manageable level. decimation the comb filter performs the first-stage filtering of the analog front-ends quantized and noise-shaped output and decimates the input sample rate by a factor of 16:1. the z-domain transfer function for the comb filter is expressed by h ( z ) = (1 z 16 ) (1 z 1 ) 4 4 the frequency domain equivalent transfer function is h ( f ) = 1 16 sin (16 p ft ) sin ( p ft ) ? ? 4 where t = 1/ f s f s = the input sample rate for the analog front end f s = (maximum 6.4 mhz).
AD776 rev. a C7C 1.0 ?.0 60 ?.4 ?.8 12 ?.6 0 0.2 ?.2 0.0 0.4 0.6 0.8 48 36 24 frequency ?khz log magnitude ?db figure 6. fir filter, compensation function the passband and stopband frequencies of both the comb and fir filters scale linearly with the clkin frequency, as shown in table i. table i. fir and comb filter characteristics clkin passband stopband (mhz) (khz) (khz) 12.8 45.5 50 12.288 43.7 48 11.2896 40.1 44.1 10.0 35.5 39.1 6.4 24.6 27.1 analog input the input to the AD776, as previously described in the discus- sion of the analog front end, uses a switched-capacitor struc- ture. as a result, the input impedance of ain+ and ainC will vary with clock frequency. table ii gives the typical analog in- put impedance for some common clkin frequencies. the input impedance is equal to ? 10 12 /3f clkin , where f clkin is the input clock rate. table ii. analog input impedance output analog input sample input clock rate rate (khz) impedance (mhz) (fir filter mode) (k v ) 12.8 100 26 6.4 50 52 6.144 48 54.3 5.6448 44.1 59 the AD776 is designed to accept input signals of (2 v ref ) C0.5 v which can be centered at various dc offsets (common- mode inputs) as long as the signal peaks are bounded by +4.0 v and 0 v. signal peaks outside this range will result in signal clipping and increased distortion products. capacitive coupling between the clkin and ain pins can cause degradation to dynamic performance. special care should be taken with respect to the layout of the clock and analog inputs. the attenuation characteristics of the comb filter are shown in figure 4. as illustrated, the frequency response in the passband region exhibits a nonflat behavior. in the 400 khz mode, the output of the comb filter provides conversion data. the dy- namic range is equivalent to approximately 72 db, or 12 bits, in this mode. in the 16-bit/100 khz mode, the comb filter serves as the input to the fir filter. the fir filter compensates for the passband roll-off of the comb filter and provides the final sharp cutoff required for stopband attenuation, removing the out-of- band noise components while partially serving as the system antialiasing filter. 0 ?00 1600 ?0 ?0 200 ?0 0 ?0 ?0 ?0 ?0 ?0 ?0 1400 1200 1000 800 600 400 frequency ?khz log magnitude ?db figure 4. comb filter response figure 5 illustrates the low-pass response of the fir filter and figure 6 shows the compensation function of the filter. the 255-tap fir filter is low-pass with 9% transition-band, and with a clkin frequency of 12.8 mhz has a 45.5 khz passband cut- off frequency, 50 khz stopband frequency, 0.001 db passband ripple, and a stopband ripple of 96 db. 0 ?20 200 ?6 0 ?8 ?2 ?4 160 120 80 40 frequency ?khz log magnitude ?db 0 45.5khz 0.001db passband ripple figure 5. fir filter, low-pass response
AD776 C8C rev. a in consideration of the dynamic characteristics of the analog input, an external op amp is generally required to provide a low impedance drive. care should be taken with op amp selection; even with modest loading conditions, most available op amps do not meet the low distortion requirements necessary to match the performance capabilities of the AD776. the ad712 op amp is a good choice for low noise and low distortion. single-ended input configurations the differential input of the AD776 provides a choice of several different input connections. figure 7 shows a simple configura- tion for a single-ended input. ainC is nom inally biased at +2.5 v by resistively dividing the +5 v power supply (av dd ). since the analog input impedance is a function of the input clock rate, determination of bias resistor values to achieve a particular bias voltage will vary with clock rate and av dd . the circuit shown in figure 7 is a low cost, minimal component solution, but may suffer from poor power supply rejection as noise present on the power supply could be coupled directly into the ainC pin. an improved input circuit is shown in figure 8, when the offset voltage is derived from the ad680 voltage refer- ence. the ad680 has 40 m v/v line regulation which results in only a 20 m v error due to 10% supply fluctuation. this improves power supply rejection of ainC input to approximately 88 db. 5 6 7 12 11 10 9 1 18 8 3 2 4 0.1? 100? 10? 47k fsi clkin 47k 10? ain+ ain dv dd av dd agnd fso dout clk dout fsel sf 13 dgnd doe to processor +5v v p-p ref AD776 10 19 refout refin 20 100? w w w figure 7. simple single-ended input circuit 3 2 0.0047 m f 47k w 47 m f ain+ ain +5v v p-p ref AD776 ad680 22 m f 100 w 0.1 m f 100 w 47 w <2 x figure 8. single-ended input circuit for improved psrr for optimal performance in single-ended input applications, the circuit in figure 9 may be used to convert the input to a differ- ential signal. v ref 2 19 ain ain+ AD776 3 refout 1k w 75 w 0.01 m f 4.99k w ad712 ad712 ad680 +5v 0.1 m f 20 refin nc = no connect 100 m f 300 w + 4.99k w (npo) 0.01 m f 10 m f + + 10 m f 4.99k w 50 w 4.99k w 10 m f 50 w figure 9. single-ended input to differential circuit reference input the AD776 has an on-chip 0.4 v dd reference voltage circuit which can be used to drive refin, as shown in figure 10. alternately, an external voltage reference may be used to supply the required 2 v. refin exhibits characteristics similar to the analog input in that the input impedance is a function of the clock rate. this is illustrated in table iii. the minimum refer- ence impedance is equal to 10 12 /2.5 f clk , where f clk is the input clock rate. table iii. reference input impedance reference input output input clock rate sample impedance (mhz) rate (khz) (k w min) 12.8 100 31.3 6.4 50 62.5 6.144 48 65.1 5.6448 44.1 70.9 19 20 100 m f refin refout AD776 figure 10. simple reference voltage circuit while the internal reference will be adequate for most applica- tions, power supply rejection and overall regulation may be improved through the use of an external reference. the process of selecting an external voltage reference should include consid- eration of drive capability, initial error, noise, and drift charac- teristics. a suitable choice would be the ad680 as shown in figure 11.
AD776 rev. a C9C 20 19 300 w 100 m f refout refin +5v AD776 ad680 0.1 m f 2.0v 75 w no connect 2.5v figure 11. external voltage reference circuit multiplexing the AD776 can also be used with an input multiplexer when the comb filter output is selected by setting fsel = 1. if f clk = 12.8 mhz, the minimum multiplex intervals are (including the time to shift the data out from the serial interface): 15 m s (if the fsi and mux are perfectly synchronized) 17.5 m s (if the fsi and mux are not synchronized). clock generation with sigma-delta converters, it is critical that clock jitter be minimized in order to achieve optimal performance. figure 12 illustrates a simple circuit used to derive a clock source for the AD776. an alternative would be to use an oscillator such as the ck1100 series from cardinal components (montclair, nj) or the f1100 from fox electronics. compared with performance obtained with a typical crystal, use of an oscillator improves snr by approximately 4 db. to AD776 pin 4 (clkin) 74hcu04 74hcu04 68pf 330 6.144mhz 470k 68pf w w figure 12. basic clock circuit board layout designing with high resolution data converters requires careful attention to board layout. trace impedance is a significant is- sue. a 1.22 ma current through a 0.5 w trace will develop a voltage drop of 0.6 mv, which is 20 lsbs at the 16 bit level for a 2 v full-scale span. in addition to ground drops, inductive and capacitive coupling need to be considered, especially when high accuracy analog signals share the same board with digital signals. analog and digital signals should not share a common return path. each signal should have an appropriate analog or digital return routed close to it. using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. wide pc tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. separate analog and digital ground planes are also desirable, with a single interconnection point at (or under) the part to minimize ground loops. this is preferred to interconnecting the grounds at the supplies. analog signals should be routed as far as possible from digital signals and should cross them, if at all, only at right angles. the AD776 may be treated as an analog component, with both agnd and dgnd connected to a single analog ground plane. this helps to isolate the AD776 from large digital ground cur- rents. for these reasons, the use of wire wrap circuit construc- tion will not provide adequate performance; careful printed circuit board construction is preferred. power supplies and decoupling with high performance linear circuits, changes in the power supplies can produce undesired changes in the performance of the circuit. optimally, well regulated power supplies with less than 1% ripple should be selected. the ac output impedance of a power supply is a complex function of frequency, but in gen- eral will increase with frequency. high frequency switching such as that encountered with digital circuitry requires fast transient currents which most power supplies cannot adequately provide. this results in voltage spikes on the supplies. to compensate for the finite ac output impedance of the supplies, it is necessary to store reserves of charge in bypass capacitors. these capaci- tors can effectively lower the ac impedance presented to the AD776 power inputs which in turn will significantly reduce the magnitude of the voltage spikes. decoupling capacitors, typi- cally 0.1 m f, should be placed as close as possible to each power supply pin of the AD776. it is essential that these capacitors be placed physically close to the AD776 to minimize the induc- tance of the pcb trace between the capacitor and the supply pin. additionally, it is beneficial to have large capacitors (>47 m f) located at the point where the power connects to the pcb with 10 m f capacitors located in the vicinity of the adc to further reduce low frequency ripple. the AD776 may be operated from a single +5 v supply. how- ever, performance is optimized by using separate analog (av dd ) and digital (dv dd ) supplies. separate supplies enable isolation of digital noise from the analog circuitry. when separate sup- plies are used, av dd should be decoupled to analog ground (agnd) and dv dd should be decoupled to digital ground (dgnd) with decoupling capacitors. when a single +5 v supply is used, the circuit shown in figure 13 provides adequate decoupling. +5v AD776 0.1 m f 10 m f av dd dv dd 0.01 m f ferrite bead 10 w 0.1 m f figure 13. single supply decoupling
AD776 C10C rev. a digital timing the clkin frequency and the choice of output filter mode (fir or comb) determine the output sample rate of the AD776. with fsel low, the fir filter output is selected and the out- put rate is equal to clkin divided by 128 . when fsel is high, the comb filter is selected and the output sample rate is equal to clkin divided by 32 . the input sample rate (or mod- ulator frequency) is always the clkin frequency divided by 2 . the flexible serial data output interface of the AD776 may be configured in one of three modes. mode a and mode b are used when the fir filter output is desired. mode c should be selected when output from the comb filter is used. output data is always transmitted as 16-bit twos complement, msb first, se- rial words. in all modes, the fsi pin may be asserted to reset the serial data output and synchronize internal circuits. a doe pin is available to place the dout pin in a high impedance state. configuring the appropriate timing mode is controlled by the fsel and sf pins. the truth table is shown in table iv. table iv. timing mode truth table fsel sf output mode 00a 01b 10c mode a the timing diagrams for mode a are shown in figures 14a and 14b. if mode a is selected, an internal multiplexer routes serial data from the output of the fir filter to the dout pin. the output sample rate is a function of the clock present at the clkin pin where: output sample rate = clkin /128 a continuous serial output clock, dout clk, is available with the bit rate determined by: dout clk = clkin/4 . serial data from the dout pin is valid on the falling edges of dout = clk. a framing signal, fso, occurs with a period equal to the output sample rate (figure 14b). the fso signal is high during the falling edge of dout clk prior to the beginning of a new output data word. clkin fsi dout clk fso dout t io t dh t fsohc t fsohc t dsu d15 d14 d13 d1 d0 zero (after previous d0) 4 t clk t clk figure 14a. mode a timing clkin dout clk fso dout valid for first 16 dout zero for last 16 dout valid 128 t clk cycles 32 dout clk cycles figure 14b. mode a timing
AD776 rev. a C11C mode b the timing diagrams for mode b are shown in figures 15a and 15b. if mode b is selected, the internal multiplexer routes serial data from the output of the fir filter to the dout pin similar to mode a. the output sample rate is a function of the clock present at the clkin pin where: output sample rate = clkin/128. a continuous serial output clock, dout clk, is available with the bit rate determined by: dout clk = clkin/4. note that serial data present at the dout pin is valid on the rising edges of dout clk. the framing signal, fso, occurs with a period equal to the output sample rate. in mode b, the fso signal goes low at the beginning of the output data word and remains low until the entire word is transmitted. clkin fsi dout clk fso dout d15 d14 d13 d0 low for d15 - d0 zero (after previous d0) t dh 8 t clk t fsosd t dsu t fsohd t clk d1 figure 15a. mode b timing dout clk fso dout 32 dout clk cycles valid for first 16 dout clk cycles zero for last 16 dout clk cycles valid low (asserted) for first 16 dout clk cycles high (deasserted) for last 16 dout clk cycles 32 dout clk cycles figure 15b. mode b timing mode c the timing diagrams for mode c are shown in figure 16. if mode c is selected, the internal multiplexer routes serial data from the output of the comb filter to the dout pin, bypass- ing the fir filter. the output sample rate is a function of the clock present at the clkin pin where: output sample rate = clkin/32. a continuous serial output clock, dout clk, is available with the bit rate determined by: dout clk = clkin/2 . serial output data is valid on the falling edges of dout clk. the framing signal, fso, occurs with a period equal to the out- put sample rate. the fso signal is high during the falling edge of dout clk prior to transmission of the next output data word. note that in mode c, this is also when the lsb, (d0), of the previous data word is valid. clkin fsi dout clk fso dout t dh t dsu d15 d14 d13 d1 d0 t fsil t io d15 d1 d0 32 dout clk cycles figure 16. mode c timing
AD776 C12C rev. a c1671C24C1/93 printed in u.s.a. fsi operation a frame sync input is available to the user on the fsi pin to reset the serial data output and synchronize internal circuits. referring to figure 17, the fsi pin is sampled on the falling edge of clkin. the fsi pin must adhere to several conditions depending on which mode is being used as follows: fsi in mode a, mode b 1. fsi should be a periodic signal occurring every 32 dout clk periods. 2. fsi must be deasserted for at least 2 clkin periods prior to being asserted. 3. fsi must be synchronized to clkin to meet the timing re- quirements outlined in figure 17. fsi in mode c 1. fsi should be a periodic signal occurring every 16 dout clk periods. 2. fsi must be deasserted for at least 2 clkin periods prior to being asserted. 3. fsi must be synchronized to clkin to meet the timing re- quirements outlined in figure 17. clkin fsi dout clk t fss t d t cl t ch t clk t ckout t dod t dod t fsh t r , t f figure 17. frame sync input (fsi) timing (fir filter out- put mode) synchronizing two channels the fsi pin is useful when multiple AD776s are used together and must be synchronized. in such a case, a single pulse may be applied to fsi inputs of the converters. this causes the internal state-machine of the AD776 to be reset. thus, the internal clocking for both the analog and digital circuitry of each individual converter is synchronized and inphase. in the case of a single fsi pulse, it must still adhere to the timing outlined in figure 17. three-stating the dout pin ( doe ) in all modes dout may be three-stated using the doe pin. operation of the doe input is shown in figure 18. when the doe input is high, serial data will be present and active at the dout pin. when doe is brought low, the dout pin is placed in a high-impedance state. doe is completely asynchro- nous and independent of input and output clocks. dout load- ing will affect actual performance. t dd t df doe data out figure 18. data output timing interfacing the AD776 the AD776 is designed for ease of interface with a variety of popular processors. the following diagrams illustrate typical configurations: fso dout dout clk doe sf AD776 rfs0 dr0 sclk0 adsp-21xx logic 0 pc5/fsr pc7/srd pc6/sck dsp56001 fsr dr clkr tms320c25 fso dout dout clk doe sf AD776 logic 0 fso dout dout clk doe sf AD776 logic 0 figure 19. outline dimensions dimensions shown in inches and (mm). 20-pin cerdip (q-20) 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 15 0 pin 1 0.310 (7.87) 0.220 (5.59) 10 11 1 20 1.060 (26.92) max 0.200 (5.08) max 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) seating plane 0.100 (2.54) bsc

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